Advanced Peripheral Bus (APB) Modelling and Verification by SystemC

The SoC (System on Chip) uses AMBA (Advanced Microcontroller Bus Architecture) as an on-chip bus. APB (Advanced Peripheral Bus) is one of the components of the AMBA bus architecture. APB is low bandwidth and low-performance bus used to connect the peripherals like UART, Keypad, Timer, and other peripheral devices to the bus architecture. The signal level model implementation of APB as per AMBA is as follows: 

* APB bridge acts as a master to the slow peripherals, devices, etc.. and these devices act as slaves to the APB master bridge. 

* APB takes data, address, preset signals from the main ASB/AHB bus and sends the same address, data to the slave via ports and signals acting as a bus.

* In the model, the master gives mainly P_ADDR, P_WRITE, PW_DATA, P_SEL, P_ENABLE, and clock input to the slave side and takes H_READY, PSLV_ERR, PR_DATA from the slave side. - Read / Write transactions occur in three states basically: IDLE, SETUP, ACCESS - In the IDLE state, P_SEL =0, P_ENABLE =0, which shows transfers is happening. 

* Whenever there is some requirement for doing transactions, the Master enters the SETUP phase and makes the PSEL line to the particular line HIGH to perform transactions with a particular slave.

* Which P_SELn should be made HIGH is decided by the address decoder in the bus arbiter. 
* In the setup phase we write the address, data onto the designated address and data bus (P_ADDR, PW_DATA), and Control signals or P_WRITE are also given based on the type of transaction. 

* After exactly one clock cycle Master enters the ACCESS state, and after getting the H_READY signal from the slave, slave Read/ Write occurs from the PW_DATA or PR_DATA. - Slave throughs an error signal PSLV_ERR if there is any error occurs during the transaction. 

* After completion of the transaction Master again comes to the IDLE state and the bus waits for the next transaction to be initiated.

22 Oct 2019


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